The present invention relates generally to a delay clock pulse-width adjusting circuit, and more particularly to a delay clock pulse-width adjusting circuit which is consisted of a delay comparator and a converting circuit, which converts the duty-ratio of a clock signal to a DC level.
In a modern signal processing system, a clock signal is indispensable. Along with the rapid development of some technical fields such as the communication, the requirement of a clock signal is getting higher. The main requirements are shown in the followings:
(1) The high frequency accuracy of a clock signal, which is solved by using a crystal oscillator or atomic clock;
(2) The long time stability of a clock signal, it is required that for one year or even longer there is only one second error or lower than one second error of a clock signal; this is solved by the clock source stability;
(3) The duty-ratio stability of a clock signal, the larger duty-ratio deviation of a clock signal can cause a larger error rate in a communication system. In an A/D converter, a sample rate in a sample/hold circuit is defined at design stage. If the duty-ratio of a clock signal changes, charging time for some capacitors will be decreased, so converting accuracy will be lower than the requirement.
FIG. 1 is a schematic diagram of a present clock generator. As shown in FIG. 1, a duty-ratio change of the clock signal mainly comes from two aspects: a system error and a random error. The system error includes a voltage amplitude change of the crystal oscillator output, a harmonics produced by loads of the clock, a change of the DC trigger level and the temperature drift etc. The random error mainly comes from the followings: a DC component deviation of the sine wave output of a crystal oscillator, a random deviation in the comparator input grade and a deviation of the DC triggering level etc.
To simplify the analysis process, all the errors are converted to a sine output of the crystal oscillator. Also, suppose a signal deviation is smaller; i.e. when analyzing error influence on a duty-ratio, according to the sine wave equation, change of a trigger time is:
xcex94V=V sin(2nfxc3x97xcex94t)xe2x80x83xe2x80x83(1)
Wherein V is amplitude of the sine wave, f is a frequency and xcex94V is a DC component change of the sine wave. Suppose V greater than  greater than xcex94V, according to the approximate equation of a sine function, from formula (1) the change of a trigger time can be approximately expressed by:
xcex94t=xcex94VIVxc3x972nfxe2x80x83xe2x80x83(2)
Since trigger time is same for leading triggering edge and falling triggering edge, so according to formula (2) change of the duty-ratio can be expressed as:
xe2x80x83xcex94D=xcex94VInVxe2x80x83xe2x80x83(3)
From formula (3), the signal, shown in FIG. 2, can be obtained.
It is seen from FIG. 2 that for the ideal clock signal if duty=t2/(tl+t2), then the signal DC level is consistent with the DC component of the sine wave. For the real clock signal, the DC trigger level is not consistent with the DC component of the sine wave, as shown by real line and dot line in FIG. 2 respectively. In FIG. 2, DC component change of the sine wave outputted by the crystal oscillator is a negative polarity, but in real, changing polarity can be positive or negative.
The purpose of the invention is to provide a delay clock pulse-width adjusting circuit which can be used in a clock signal circuit for intermediate frequency or high frequency. With this adjusting circuit, the duty-ratio of a clock signal is no larger abrupt change, so burden of the digital signal processing is decreased. The adjusting circuit also is suitable for submicron integrated circuit technology, so it will decrease influence of the random error during chips manufacturing process. Consequently, the adjusting circuit makes chips of digital-analog hybrid integrated circuit satisfy the requirement: high traffic, low error rate and high stability of the clock signal duty-ratio.
For the purpose mentioned above, the invention first provides a delay clock pulse-width adjusting circuit for intermediate frequency or high frequency with a delay comparator and a power supply. It is important that the adjusting circuit also includes:
One input terminal of the delay comparator inputs a sine wave signal which compares with a voltage inputted from another input terminal of the delay comparator, and the output is a defined duty-ratio clock signal; and
A converting circuit converts a clock signal duty-ratio to a DC level. Input terminal of the converting circuit is connected to output terminal of the said delay comparator, and output of the converting circuit is a DC level which is converted from the said clock signal. Again, output terminal of the converting circuit is connected to another input terminal of the said delay comparator.
Said converting circuit is mainly consisted of a Pulse-Width Modulation (PWM) filter module, which converts a clock signal to a DC level.
Said converting circuit is mainly consisted of a pulse-width modulator (PWM) filter module and a low pass filter circuit. The PWM filter module converts a clock signal to a DC level. The low pass filter circuit filters the DC level outputted from the PWM filter module then outputs to the delay comparator as an input.
Said low pass filter is a transconductance operational amplifier.
Said PWM filter comprises an inverter, whose input is a clock signal and output is an inverted clock signal; first switch, which is controlled by the inverted clock signal; second switch, which is controlled by the clock signal; first current source, which is connected to the supply with one end and to the first switch with another end; second current source, which is connected to the ground with one end and is connected to a node A with another end; third current source, which is connected to the ground with one end and to the second switch with another end; first current mirror, which is connected to the second switch with one end and is connected to the supply with another end; second current mirror, which is connected to the supply with one end and to the output with another end, and a current to voltage converter, which is connected to the ground with one end and to the output with another end.
Said first switch is an OR gate consisted of a pair of PMOS transistors, and said second switch is an OR gate consisted of a pair of NMOS transistors. Said a current mirror is consisted of two MOS transistors with the connections as follow: the drain and gate of one MOS transistor is connected with the gate of another MOS transistor, the sources of the two MOS transistors are connected with the supply, and the drain of another MOS transistor is the output. Said current to voltage converter is a capacitor.
Said converting circuit at least includes:
A detection circuit is used to detect whether the input clock signal, which is the output of said delay comparator, exists a floating signal and to output a voltage difference according to the floating signal; and
A correction circuit is used to correct the threshold voltage input of said delay comparator according to the voltage difference output of the detection circuit.
Said detection circuit has an inverter, which inverts an input clock signal to output an inverted clock signal; a current switch, which is controlled by the clock signal and inverted clock signal; first current mirror circuit, which is connected with one input of the current switch and charges the capacitor of the correction circuit when the clock signal is a high level; second current mirror circuit, which is connected to another input of the current switch; and third current mirror circuit, which is connected with second current mirror circuit and discharges the capacitor of the correction circuit when the clock signal is a low level.
Said detection circuit also has a current source circuit used to provide a bias current to the current switch.
There is another detection circuit. The detection circuit at least includes an inverter, which inverts the input clock signal and outputs an inverted clock signal; first and second current switches, which are serially connected with each other and are controlled by the clock signal and the inverted clock signal; first current source circuit, which is connected to the supply with one end and to the first current switch with another end, and charges the capacitor of the correction circuit when the clock signal is a high level; and second current source circuit, which is connected to the second current switch with one end and to the ground with another end, and discharges the capacitor of the correction circuit when the clock signal is a low level.
Said current switch is an OR gate of two MOS transistors. Said current mirror circuit is connected as follow: the drain and gate of one MOS transistor are connected with the gate of another MOS transistor, the sources of the two MOS transistors are connected with the supply, and the drain of another MOS transistor is the output.
The correction circuit is consisted of a current to voltage converting circuit and a comparative circuit. The said correction circuit is a current source circuit consisted of an operational amplifier, a NMOS transistor and a resistance. The said current to voltage circuit is consisted of a MOS transistor and a capacitor.
The invention also provides two schemes for long delay processing.
A long delay clock pulse-width adjusting circuit for intermediate or high frequency has a delay comparator and more than one kind of power supplies. The adjusting circuit includes:
One input of the said delay comparator is connected with a sine wave and compared with another input connected with a DC level, and the output of the said delay comparator is a clock signal with a defined duty-ratio;
A PWM filter module converts a clock signal to a DC level, whose input is connected to the delay comparator output, and whose output is connected to the another input of the delay comparator.
Said PWM filter module has an inverter, which inverts an input clock signal to output an inverted clock signal; first switch, which is controlled by the inverted clock signal; second switch, which is controlled by the clock signal; first current source, which is connected to the supply with one end and to the first switch with another end; second current source, which is connected to the ground with one end and to a node A with another end; third current source, which is connected to the ground with one end and to the second switch with another end; first current mirror, which is connected to the second switch with one end and to the supply with another end; second current mirror, which is connected to the supply with one end and to the output with another end; and a current to voltage converter, which is connected to the ground with one end and to the output with another end.
Said first switch is an OR gate consisted of a pair of PMOS transistors, and said second switch is an OR gate consisted of a pair of NMOS transistors. A said current mirror is connected as follow: the drain and gate of one MOS transistor are connected with the gate of another MOS transistor, the sources of two MOS transistors are connected with the supply and the drain of another MOS transistor is an output. Said a current to voltage converter is a capacitor.
A long delay clock pulse-width adjusting circuit for intermediate or high frequency has a delay comparator and more than one kind of power supplies. The adjusting circuit includes:
One input of the said delay comparator is connected with a sine wave and compared with another input connected with a DC level, and the output of the said delay comparator is a clock signal with a defined duty-ratio;
A PWM filter module converts a clock signal to a DC level, whose input is connected to the delay comparator output; and
A low pass filter circuit filters the output DC level of said PWM filter module and the output of the filter is used as the input DC level of said delay comparator.
Said low pass filter circuit is a transconductance operational amplifier.
Said PWM filter module has an inverter, whose input is a clock signal and output is an inverted clock signal; first switch, which is controlled by the inverted clock signal; second switch, which is controlled by the clock signal; first current source, is connected to the supply which with one end and to the first switch with another end; second current source, which is connected to the ground with one end and to a node A with another end; third current source, which is connected to the ground with one end and to the second switch with another end; first current mirror, which is connected to the second switch with one end and to the supply with another end; second current mirror, which is connected to the supply with one end and to the output with another end; and a current to voltage converter, which is connected to the ground with one end and to the output with another end.
Said first switch is an OR gate consisted of a pair of PMOS transistors, and said second switch is an OR gate consisted of a pair of NMOS transistors. A said current mirror is connected as follow: the drain and gate of one MOS transistor are connected with the gate of another MOS transistor, the sources of two MOS transistors are connected with the supply and the drain of another MOS transistor is an output. Said a current to voltage converter is a capacitor.
The invention also provides a short delay clock pulse-width adjusting circuit for intermediate or high frequency, which has a delay comparator and a power supply. The adjusting circuit includes:
One input of the said delay comparator is connected with a sine wave and compared with another input connected with a threshold voltage, and the output of the said delay comparator is a clock signal with a defined duty-ratio;
A detection circuit is used to detect whether the input clock signal, which is the output of said delay comparator, exists a floating signal and to output a voltage difference according to the floating signal; and
A correction circuit is used to correct the clock signal according to the voltage difference output of the detection circuit, which output terminal is connected to the another input terminal of the delay comparator.
Said detection circuit has an inverter, which inverts an input clock signal and outputs an inverted clock signal; a current switch, which is controlled by the clock signal and inverted clock signal; first current mirror circuit, which is connected to one input of the current switch and charges the capacitor of the correction circuit when the clock signal is a high level; second current mirror circuit, which is connected to another input of the current switch; and third current mirror circuit, which is connected to the second current mirror circuit and discharges the capacitor of the correction circuit when the clock signal is a low level.
Said detection circuit also has a current source circuit used to provide a bias current to the current switch.
There is another detection circuit. The detection circuit at least includes an inverter, which inverts the input clock signal to output an inverted clock signal; first and second current switches, which are serially connected with each other and are controlled by the clock signal and the inverted clock signal; first current source circuit, which is connected to the supply with one end and to the first current switch with another end, and charges the capacitor of the correction circuit when the clock signal is a high level; and second current source circuit, which is connected to the second current switch with one end and to the ground with another end, and discharges the capacitor of the correction circuit when the clock signal is a low level.
Said current switch is an OR gate of two MOS transistors. Said current mirror circuit is connected as follow: the drain and gate of one MOS transistor are connected with the gate of another MOS transistor, the sources of the two MOS transistors are connected with the supply, and the drain of another MOS transistor is the output.
The correction circuit is consisted of a current to voltage converting circuit and a comparative circuit. The said correction circuit is a current source circuit consisted of an operational amplifier, a NMOS transistor and a resistance. The said current to voltage converting circuit is consisted of a MOS transistor and a capacitor.
The invention can deal with pulse-width adjustment of a long delay clock signal with lower than 200 MHz frequency. Through filtering the pulse-width modulation signal, a DC level, which is proportional to the duty-ratio of a clock signal, can be obtained. In general, the clock signal has higher frequency, such as higher than 10 MHz, so the invention has designed a filter for this requirement.
The invention, a delay clock pulse-width adjusting circuit for intermediate or high frequency, takes a sine wave through a delay comparator to produce a clock signal. The output of the delay comparator is a clock signal, whose duty-ratio can be slowly changed, and whose output, which is used as a pulse-width modulation signal, is inputted to a converting circuit. The output of the converting circuit, which is used as a DC comparative level, is inputted to the delay comparator. Therefore, the DC comparative level of the delay comparator is floating; but in the present circuit, the DC comparative level is fixed.
During working period of the adjusting circuit, the DC level of the delay comparator will follow the DC component of a sine wave, which changes slowly. The output duty-ratio of the delay comparator will slowly approach to a preset value until the DC comparative level of the delay comparator has completely compensated the DC component of the sine wave, which has abruptly changed. The duty-ratio of the clock signal will recover to the preset value. The duration can be several tens to several hundreds clock cycles, which depends on a specific situation.
Consequently, the adjusting circuit of the invention can solve the duty-ratio of a clock signal slowly changing problem. The duty-ratio changing is a system error and a random error, which are caused by such as devices dismatch during manufacturing, strength uneven distribution during packing, temperature changing and low frequency noise, etc.
Although, in the above description, the DC component of a sine wave is abruptly changed, but the description is also suitable for a gradually changing situation.
The adjusting circuit of the invention can also deal with a short delay clock signal under 400 MHz. In this case, the duty-ratio of a clock signal is set to a defined value. Any change, deviating the defined value no matter it is an abrupt change or a gradual change, will be detected and corrected immediately. The correction duration is one to two clock cycles.
The detected circuit of duty-ratio, uses two kind of structures to solve a bottleneck problem of the integrate circuit response speed. Within one of which, correcting is made by using equity constant-current source method.
In the short delay processing circuit of the invention, the output clock signal is directly used in the detection circuit, so the devices dismatch influence caused by integrated circuit manufacturing is eliminated.
Although the duty-ratio adjusting circuit of a clock signal is designed for the quick response of a abrupt changing, but it also can be used in a gradually changing situation.
In summary, the invention, a delay clock pulse-width adjusting circuit for intermediate or high frequency, can deal with a long delay or short delay clock signal. The output of the adjusting circuit is a clock signal with stable duty-ratio, and the design of the adjusting circuit is suitable for submicron integrated circuit technology. Consequently, the adjusting circuit makes system of digital-analog hybrid satisfy the requirement: high traffic, low error rate and high stability of the clock signal duty-ratio.